TXXOS

The Channel Status Word (CSW) is used to provide the status of an I/O device or the status of the last I/O operation completed.  The CSW is updated when an I/O interruption occurs or as a result of an I/O command.  The CSW is available for use until the next I/O interrupt occurs or until another I/O command causes it to be replaced.

When an I/O interruption updates the CSW the I/O device causing the interruption is identified in the Old PSW as the interruption code when operating in BC mode.

The CSW has the following format:

Protection Key (Bits 0-3) indicates the protection key used for the I/O operation.

Logout Pending (L) (Bit 5) When set to one it indicates that an I/O instruction cannot be executed until a pending logout condition has been cleared.

Deferred Condition Code (CC) (Bits 6-7) Indicate a different condition code available for a Start I/O Fast Release after a condition code of zero was returned.

CCW Address (Bits 8-31) Indicate an address eight bytes greater than the last CCW used.

Status (Bits 32-47) These bits identify the condition that caused the CSW to be stored.

• 32 Attention – The device has detected an asynchronous condition significant to the program
• 33 Status Modifier – Indicates the device cannot provide its current status in response to a TEST I/O, when the control unit is busy, when the normal sequence of commands has to be modified or when command retry is to be initiated.
• 34 Control Unit End – Indicates the control unit has become available for use for another operation.
• 35 Busy – Indicates the I/O device cannot execute the command because it is executing a previously initiated operation or because there is a pending interrupt condition.
• 36 Channel End – Indicates completion of the portion of an I/O operation involving the transfer of data or control information between the I/O device and the channel.  When command chaining is used Channel End is generated only for the last operation.
• 37 Device End – Indicates the completion of an I/O operation by the device.  When command chaining is used only the Device End condition for the last operation in the chain is reported.
• 38 Unit Check – Indicates the I/O device or control unit has detected an unusual condition and additional detail information is available to a sense command.
• 39 Unit Exception – Indicates a condition reported by an I/O device that does not usually occur.
• 40 Program Controlled Interruption – This condition is generated when a channel fetches a CCW with the PCI flag set.
• 41 Incorrect Length – Indicates the number of bytes in storage assigned to the I/O operation is not equal to the number of bytes requested by the device.
• 42 Program Check – Indicates a programming error in the channel program.  Can occur as a result of an invalid address in the CAW or a TIC CCW, an invalid command code, an invalid count in a CCW, an invalid data address, an invalid CAW format, an invalid CCW format or an invalid sequence of CCWs.
• 43 Protection Exception – Indicates the channel attempted to access storage that is prohibited by storage protection.
• 44 Channel Data Check – Indicates a machine error has occurred causing a parity error.
• 45 Channel Control Check – Indicates a machine error.
• 46 Interface Control Check – Indicates an invalid signal occurred on the I/O interface.
• 47 Chaining Check – Indicates a channel overrun during data chaining operations.

Count (Bits 48-63) Contain the residual count for the last CCW.

[Next – I/O Machine Instructions]

The sense command is used to receive both the status of the device and any information about any unusual or error condition for the last operation of the device.

Although sense information is specific to each device usually the first six bits of sense data give information about the conditions detected in the last operation.

Command Reject (Bit 0) indicates the device has detected a programming error.  The device is unable to execute the command because it is invalid for the device or the device cannot currently execute the command (for example the device is write protected).  Command reject can also indicate an invalid sequence of commands.

Intervention Required (Bit 1) The operation could not be executed because the device requires some type of intervention (for example printer needs paper) or the device is in a not ready state.

Bus Out Check (Bit 2) The device has received data with an invalid parity.

Equipment Check (Bit 3) Indicates the device has detected an equipment malfunction.

Data Check (Bit 4) Indicates the device has detected a data error other than those causing a Bus Out Check.

Overrun (Bit 5) Indicates the channel has failed to respond on time to a request from the device.

The final type of CCW command code is the Transfer In Channel (TIC).  It is a branching instruction for the channel command.  Normally when  command chaining is active CCWs are executed sequentially.  A TIC will cause the next CCW to be fetched from the data location specified by the data address in the TIC CCW.  The first CCW pointed to by the CAW cannot be TIC nor can a TIC specify a branch to another TIC CCW.

[Next – Channel Status Word]

Each CCW is 64 bits (8 BYTES) in length and has the following format:

Command Code (Bits 0-7) Specifies the I/O operation to be performed.

Data Address (Bits 8-31) Specifies the location in main storage for the data associated with the I/O operation.

Chain Data Flag (CD) (Bit 32) When set to one indicates the chaining of data.  It causes the storage area of the next CCW to be used with the current I/O operation.  The use of data chaining allows data to be transferred to or from noncontiguous areas of storage in a single I/O operation.

Command Chain (CC) (Bit 33) When set to one, and when the CD flag is set to zero, indicates the chaining of commands.  When the operation of the current CCW is complete and Command Chaining is active, the next CCW will become the new current I/O operation.

Suppress Length Indication (SLI) (Bit 34) When set to one and the CD flag is set to zero, the incorrect length indication is suppressed.

Skip (SKIP) (Bit 35) When set to one the transfer of information is suppressed for read and sense operations.

Program Controlled Interrupt (PCI) (Bit 36) When set to one the channel will generate an interruption condition when the CCW begins execution in the channel.

Indirect Data Address (IDA) (Bit 37) When set to one indicates indirect addressing.  The data address of the CCW points to an Indirect Address List instead of directly to the data.

Count (Bits 48-63) Specifies the number of bytes to be used for the I/O operation.

Bits 38-47 should always be set to zeros.

Channel command codes are specific to each individual device but fall into general categories: Write, Read, Read Backward, Control and Sense.  Write transfers data from the processor storage to the device, read and read backward transfer data from the device to processor storage.  Control operations are specific to each device and generally do not involve data transfer but the data address in the CCW may point to an area in storage related to the control operation.

[Next – Sense Command]

I/O operations on S/370 are used to transfer information to and from I/O devices which are attached to channels.  There are many types of I/O devices including card readers, card punches, printers,  tape devices, terminals and disk storage devices.

A channel attached device can be thought of as a very simple computer that uses a very limited programming language.  The programming instructions are called Channel Command Words (CCW).  A CCW indicates the operation to be performed (such as read a card or print a line), the data location in the processor memory and the length of the data operation.  In addition there are some flags that may be set in the CCW to further indicate how to execute the requested operation.

Each individual device type has a set of commands that it will respond to.  An invalid command will result in an execution error of the channel program.  When writing channel programs it is necessary to know the programming specifications for each specific device being used.

An I/O operation is initiated by building a channel program consisting of one or more CCWs.  The address of the channel program is placed in a fixed position in low storage called the Channel Address Word (CAW).  An I/O operation is initiated using the Start I/O (SIO) instruction. This instruction along with all other I/O commands can only be executed when operating in privileged mode.

When the channel program is complete an I/O interrupt will be generated if interrupts are enabled.  If interrupts are disabled for the device, the interrupt will be queued.  A queued I/O interrupt can be cleared either by enabling interrupts or using the Test I/O (TIO) instruction.

When the pending I/O interrupt condition for a device is cleared the Channel Status Word (CSW) in low storage will be updated providing information on the completion status of the I/O operation.

[Next – Channel Command Word]

The interruption is a mechanism to signal the CPU when certain conditions exist. For I/O interruptions the CPU is signaled when some event happens with an I/O device such as I/O operation complete or an error condition.  By using interruptions the CPU can initiate an I/O operation and does not have to continuously check the status to see if it has completed.  Instead when the I/O operation is complete the CPU will be signaled with an interrupt.

There are several classes of interrupts defined in the System 370 architecture.  Each interrupt class has two specific locations in low memory used to hold PSWs.  When an interrupt occurs the current CPU PSW is stored in the Old PSW location for the interrupt class and is replaced with the value of the New PSW location.

By loading a New PSW the state of the CPU is changed enabling the interruption condition to be handled.  When interruption handling is complete the Old PSW can be used to restore execution of the interrupted program.

Some interruptions can be “Masked” – that is ignored depending on settings in the current PSW.  For example while an I/O interruption is being processed all other I/O interruptions should be masked until completion of the current I/O interruption processing.

The classes of interruptions are:

Machine-Check Interruption Indicates an equipment malfunction.  When this interruption occurs the Old PSW is stored in location 48 and a new PSW is fetched from location 112.

Program Interruption Results from an error during the execution of a program (such as an invalid operation code or attempt to execute a privileged instruction while in problem state).  When this interruption occurs the Old PSW is stored in location 40 and a new PSW is fetched from location 104.

Supervisor Call Interruption Occurs when a Supervisor Call (SVC) instruction is executed. When this interruption occurs the Old PSW is stored in location 32 and a new PSW is fetched from location 96.

External Interruption Signals the CPU to conditions outside the system.  These interruptions include the operator pressing the Interrupt Key or when the Interval Timer is decremented and goes from a positive value to a negative value.  When this interruption occurs the Old PSW is stored in location 24 and a new PSW is fetched from location 88.

Input/Output Interruption Allows the CPU to be notified of various conditions for I/O devices and channels.  When this interruption occurs the Old PSW is stored in location 56 and a new PSW is fetched from location 120.  In addition a Channel Status Word (CSW) is stored at location 64.

Restart Interruption Allows the CPU to respond to an interruption generated by the operator pressing the restart key.  When this interruption occurs the Old PSW is stored in location 8 and a new PSW is fetched from location 0 (zero).

[Next – Input Output Basics]

The Program Status Word (PSW) contains information about the current execution state of the processor.  Certain actions cause the complete PSW to be stored or loaded.  Others operate on only a portion of the PSW.

The Load PSW instruction (LPSW) will load a new value into the PSW and replace the old contents.  Interrupts cause the current PSW contents to be stored at a specific location and a new PSW to be loaded.  The locations for storing the old PSW and fetching the new PSW are defined in low storage with the actual address depending on the specific interrupt.

In 370 mode there are two different forms of the PSW – Basic Control (BC) and Extended Control (EC).  The BC PSW is essentially the same format as initially introduced on the System 360.  When bit 12 of the PSW is zero the PSW is in BC mode.  For now we will only concern ourselves with the BC PSW.

The BC PSW consists of 64 bits (8 bytes or 2 words) with the following layout:

Bits 0-5        Channel Masks 0-5

Bit  6          Input/Output Mask (IO)

Bit  7          External Mask (E)

Bits 8-11       Protection Key

Bit  12         BC/EC Control

Bit  13         Machine Check Mask (M)

Bit  14         Wait State (W)

Bit  15         Problem State (P)

Bits 16-31      Interruption Code

Bits 32-33      Instruction Length Code (ILC)

Bits 34-35      Condition Code (CC)

Bits 36-39      Program Mask

Bits 40-63      Instruction Address

Channel Masks 0-5 (Bits 0-5) Control whether the CPU  is enabled for I/O interruptions from channels 0-5.  When the bit is zero the corresponding channel cannot cause an I/O interruption.  When the bit is one an interruption can occur.

Input/Output Mask (IO) (Bit 6) Controls whether the CPU is enabled for I/O interruptions from channels 6 and higher.  When the bit is zero these channels cannot cause an I/O interruption.  When the bit is one interruptions may occur if the channel interruption is enabled in control register (CR) 2.  Setting the I/O mask bit in the PSW to zero has the same effect as setting all the bits in CR 2 to zero.  Initially CR 2 contains a value of one in all bits therefore enabling all interrupts on channels 6 and higher when the IO Mask bit is set to one.

External Mask (E) (Bit 7) Controls whether the CPU is enabled for external interruptions.  When set to one interruptions are enabled.

Protection Key (Bits 8-11) The protection key is compared to the page storage key when storing to memory or when fetching and the page is protected against fetching.  A PSW protection key of zero can access any page.

Extended Control Mode (Bit 12) Indicates the format of the PSW and the mode of operation of the CPU.  For Basic Control (BC) the bit is set to zero, for Extended Control (EC) the bit is set to one.

Machine Check Mask (M) (Bit 13) Controls whether the CPU is enabled for machine check interruptions.  When set to one interruptions are enabled.

Wait State (W) (Bit 14) When the Wait bit is set to one the CPU is in the wait state and no instructions are executed.  When set to zero it is in running state.

Problem State (P) (Bit 15) When set to one the CPU is in problem state and any attempt to execute a privileged instruction will fail.  When set to zero the CPU is in supervisor state.

Interruption Code (Bits 16-31) When an old PSW is stored as a result of a program, supervisor call, external or I/O interruption these bits identify the cause of the interruption.  These bits are ignored when a new PSW is loaded.

Instruction Length Code (ILC) (Bits 32-33) Indicates the length of the last executed instruction when a program or supervisor call interruption occurs or when a Branch And Link is executed.  The contents of these bits are ignored when a new PSW is loaded.

Condition Code (CC) (Bits 34-35) Condition code.

Program Mask (Bits 36-39) Each bit is associated with a program exception interruption. When the bit is zero an interruption will not occur.  Bit 36: Fixed-point overflow. Bit 37: Decimal overflow. Bit 38: Exponent underflow. Bit 39: Significance.

Instruction Address (Bits 40-63) Contains the address of the next instruction to be executed.

[ Next – Interruptions ]