Program Status Word

The Program Status Word (PSW) contains information about the current execution state of the processor.  Certain actions cause the complete PSW to be stored or loaded.  Others operate on only a portion of the PSW.

The Load PSW instruction (LPSW) will load a new value into the PSW and replace the old contents.  Interrupts cause the current PSW contents to be stored at a specific location and a new PSW to be loaded.  The locations for storing the old PSW and fetching the new PSW are defined in low storage with the actual address depending on the specific interrupt.

In 370 mode there are two different forms of the PSW – Basic Control (BC) and Extended Control (EC).  The BC PSW is essentially the same format as initially introduced on the System 360.  When bit 12 of the PSW is zero the PSW is in BC mode.  For now we will only concern ourselves with the BC PSW.

The BC PSW consists of 64 bits (8 bytes or 2 words) with the following layout:

Bits 0-5        Channel Masks 0-5
Bit  6          Input/Output Mask (IO)
Bit  7          External Mask (E)
Bits 8-11       Protection Key
Bit  12         BC/EC Control
Bit  13         Machine Check Mask (M)
Bit  14         Wait State (W)
Bit  15         Problem State (P)
Bits 16-31      Interruption Code
Bits 32-33      Instruction Length Code (ILC)
Bits 34-35      Condition Code (CC)
Bits 36-39      Program Mask
Bits 40-63      Instruction Address

Channel Masks 0-5 (Bits 0-5) Control whether the CPU  is enabled for I/O interruptions from channels 0-5.  When the bit is zero the corresponding channel cannot cause an I/O interruption.  When the bit is one an interruption can occur.

Input/Output Mask (IO) (Bit 6) Controls whether the CPU is enabled for I/O interruptions from channels 6 and higher.  When the bit is zero these channels cannot cause an I/O interruption.  When the bit is one interruptions may occur if the channel interruption is enabled in control register (CR) 2.  Setting the I/O mask bit in the PSW to zero has the same effect as setting all the bits in CR 2 to zero.  Initially CR 2 contains a value of one in all bits therefore enabling all interrupts on channels 6 and higher when the IO Mask bit is set to one.

External Mask (E) (Bit 7) Controls whether the CPU is enabled for external interruptions.  When set to one interruptions are enabled.

Protection Key (Bits 8-11) The protection key is compared to the page storage key when storing to memory or when fetching and the page is protected against fetching.  A PSW protection key of zero can access any page.

Extended Control Mode (Bit 12) Indicates the format of the PSW and the mode of operation of the CPU.  For Basic Control (BC) the bit is set to zero, for Extended Control (EC) the bit is set to one.

Machine Check Mask (M) (Bit 13) Controls whether the CPU is enabled for machine check interruptions.  When set to one interruptions are enabled.

Wait State (W) (Bit 14) When the Wait bit is set to one the CPU is in the wait state and no instructions are executed.  When set to zero it is in running state.

Problem State (P) (Bit 15) When set to one the CPU is in problem state and any attempt to execute a privileged instruction will fail.  When set to zero the CPU is in supervisor state.

Interruption Code (Bits 16-31) When an old PSW is stored as a result of a program, supervisor call, external or I/O interruption these bits identify the cause of the interruption.  These bits are ignored when a new PSW is loaded.

Instruction Length Code (ILC) (Bits 32-33) Indicates the length of the last executed instruction when a program or supervisor call interruption occurs or when a Branch And Link is executed.  The contents of these bits are ignored when a new PSW is loaded.

Condition Code (CC) (Bits 34-35) Condition code.

Program Mask (Bits 36-39) Each bit is associated with a program exception interruption. When the bit is zero an interruption will not occur.  Bit 36: Fixed-point overflow. Bit 37: Decimal overflow. Bit 38: Exponent underflow. Bit 39: Significance.

Instruction Address (Bits 40-63) Contains the address of the next instruction to be executed.

[ Next – Interruptions ]

Leave a Reply

Your email address will not be published. Required fields are marked *