Monthly Archives: June 2011

by tommy

Interruptions

The interruption is a mechanism to signal the CPU when certain conditions exist. For I/O interruptions the CPU is signaled when some event happens with an I/O device such as I/O operation complete or an error condition.  By using interruptions the CPU can initiate an I/O operation and does not have to continuously check the status to see if it has completed.  Instead when the I/O operation is complete the CPU will be signaled with an interrupt.

There are several classes of interrupts defined in the System 370 architecture.  Each interrupt class has two specific locations in low memory used to hold PSWs.  When an interrupt occurs the current CPU PSW is stored in the Old PSW location for the interrupt class and is replaced with the value of the New PSW location.

By loading a New PSW the state of the CPU is changed enabling the interruption condition to be handled.  When interruption handling is complete the Old PSW can be used to restore execution of the interrupted program.

Some interruptions can be “Masked” – that is ignored depending on settings in the current PSW.  For example while an I/O interruption is being processed all other I/O interruptions should be masked until completion of the current I/O interruption processing.

The classes of interruptions are:

Machine-Check Interruption Indicates an equipment malfunction.  When this interruption occurs the Old PSW is stored in location 48 and a new PSW is fetched from location 112.

Program Interruption Results from an error during the execution of a program (such as an invalid operation code or attempt to execute a privileged instruction while in problem state).  When this interruption occurs the Old PSW is stored in location 40 and a new PSW is fetched from location 104.

Supervisor Call Interruption Occurs when a Supervisor Call (SVC) instruction is executed. When this interruption occurs the Old PSW is stored in location 32 and a new PSW is fetched from location 96.

External Interruption Signals the CPU to conditions outside the system.  These interruptions include the operator pressing the Interrupt Key or when the Interval Timer is decremented and goes from a positive value to a negative value.  When this interruption occurs the Old PSW is stored in location 24 and a new PSW is fetched from location 88.

Input/Output Interruption Allows the CPU to be notified of various conditions for I/O devices and channels.  When this interruption occurs the Old PSW is stored in location 56 and a new PSW is fetched from location 120.  In addition a Channel Status Word (CSW) is stored at location 64.

Restart Interruption Allows the CPU to respond to an interruption generated by the operator pressing the restart key.  When this interruption occurs the Old PSW is stored in location 8 and a new PSW is fetched from location 0 (zero).

[Next – Input Output Basics]

by tommy

Program Status Word

The Program Status Word (PSW) contains information about the current execution state of the processor.  Certain actions cause the complete PSW to be stored or loaded.  Others operate on only a portion of the PSW.

The Load PSW instruction (LPSW) will load a new value into the PSW and replace the old contents.  Interrupts cause the current PSW contents to be stored at a specific location and a new PSW to be loaded.  The locations for storing the old PSW and fetching the new PSW are defined in low storage with the actual address depending on the specific interrupt.

In 370 mode there are two different forms of the PSW – Basic Control (BC) and Extended Control (EC).  The BC PSW is essentially the same format as initially introduced on the System 360.  When bit 12 of the PSW is zero the PSW is in BC mode.  For now we will only concern ourselves with the BC PSW.

The BC PSW consists of 64 bits (8 bytes or 2 words) with the following layout:

Bits 0-5        Channel Masks 0-5
Bit  6          Input/Output Mask (IO)
Bit  7          External Mask (E)
Bits 8-11       Protection Key
Bit  12         BC/EC Control
Bit  13         Machine Check Mask (M)
Bit  14         Wait State (W)
Bit  15         Problem State (P)
Bits 16-31      Interruption Code
Bits 32-33      Instruction Length Code (ILC)
Bits 34-35      Condition Code (CC)
Bits 36-39      Program Mask
Bits 40-63      Instruction Address

Channel Masks 0-5 (Bits 0-5) Control whether the CPU  is enabled for I/O interruptions from channels 0-5.  When the bit is zero the corresponding channel cannot cause an I/O interruption.  When the bit is one an interruption can occur.

Input/Output Mask (IO) (Bit 6) Controls whether the CPU is enabled for I/O interruptions from channels 6 and higher.  When the bit is zero these channels cannot cause an I/O interruption.  When the bit is one interruptions may occur if the channel interruption is enabled in control register (CR) 2.  Setting the I/O mask bit in the PSW to zero has the same effect as setting all the bits in CR 2 to zero.  Initially CR 2 contains a value of one in all bits therefore enabling all interrupts on channels 6 and higher when the IO Mask bit is set to one.

External Mask (E) (Bit 7) Controls whether the CPU is enabled for external interruptions.  When set to one interruptions are enabled.

Protection Key (Bits 8-11) The protection key is compared to the page storage key when storing to memory or when fetching and the page is protected against fetching.  A PSW protection key of zero can access any page.

Extended Control Mode (Bit 12) Indicates the format of the PSW and the mode of operation of the CPU.  For Basic Control (BC) the bit is set to zero, for Extended Control (EC) the bit is set to one.

Machine Check Mask (M) (Bit 13) Controls whether the CPU is enabled for machine check interruptions.  When set to one interruptions are enabled.

Wait State (W) (Bit 14) When the Wait bit is set to one the CPU is in the wait state and no instructions are executed.  When set to zero it is in running state.

Problem State (P) (Bit 15) When set to one the CPU is in problem state and any attempt to execute a privileged instruction will fail.  When set to zero the CPU is in supervisor state.

Interruption Code (Bits 16-31) When an old PSW is stored as a result of a program, supervisor call, external or I/O interruption these bits identify the cause of the interruption.  These bits are ignored when a new PSW is loaded.

Instruction Length Code (ILC) (Bits 32-33) Indicates the length of the last executed instruction when a program or supervisor call interruption occurs or when a Branch And Link is executed.  The contents of these bits are ignored when a new PSW is loaded.

Condition Code (CC) (Bits 34-35) Condition code.

Program Mask (Bits 36-39) Each bit is associated with a program exception interruption. When the bit is zero an interruption will not occur.  Bit 36: Fixed-point overflow. Bit 37: Decimal overflow. Bit 38: Exponent underflow. Bit 39: Significance.

Instruction Address (Bits 40-63) Contains the address of the next instruction to be executed.

[ Next – Interruptions ]

by tommy

Initial Program Load

On the IBM 360/20 there was a blue button on the CPU console labeled “IPL.”  On the 370/158 you initiated an IPL using the integrated operator console (a 3270 device with a light pen).  The end result was the same – the IPL function of the processor was invoked.

The device to be used for the IPL process is specified by the operator prior to invoking the IPL function.  It might have been specified using the dials and switches or it may have been specified on the operator console.

When the IPL function is initiated the processor issues a read command to the IPL device.  This read command reads 24 bytes of data.  Yes! That’s all, 24 bytes.  But this is enough to get the process started.

It can’t be just any 24 bytes of data.  It has to be 24 bytes of very specific data.  To understand the IPL process we have to understand two hardware data structures – the Program Status Word (PSW) and Channel Command Word (CCW).  This is because the 24 bytes read by the IPL process must be an eight-byte PSW followed by two eight-bytes CCWs.

In the next section we will explore the PSW so we have a better understanding of how to get our initial program loader up and running.

[ Next – Program Status Word ]

by tommy

Card Loader

To run a Bare Metal program we must have some way to get our program into the processor and ready for execution.  We could take the approach I used on the 370/158 that didn’t have any I/O devices except the operator console.  On that system I used the Storage Alter function to enter my program in hex.  (This was also a familiar technique used on early microprocessors)

There are a couple of problems doing this.  First is that it can be very time consuming.  Another problem is this process is very error prone – easy to get lost when entering a long string of hex.  Then there is the problem of making code changes.  You can write patches to the code already entered or you start from the beginning and enter everything again.  In my 370/158 days I avoided starting over from the beginning.  I would spend a few minutes each day adding to the existing code in memory.  As it was patched and re-patched it became difficult to keep up with.  I finally gave up when the system had to be shut down due to some maintenance to the facility.  I just couldn’t bring myself to start entering hex from the beginning.

Fortunately the designers of the System 360/370 processors give us an easier way – if we have an input device.  We can IPL from cards, tape or a disk drive.

We will begin with an IPL from a card reader since it is probably the easiest.  At least from the standpoint of an old timer like myself who is very familiar with decks of cards.

Our initial goal  is to create a small set of cards containing the necessary instructions to load an object deck into memory and cause it to begin execution.

[ Next – IPL Initial Program Load ]

by tommy

Introduction

This site is devoted to exploring how to program an IBM 370 Mainframe at the “Bare Metal” level.  This is how to program without any preexisting supervisor or operating system code.

It is assumed that the reader is familiar with the basics of the IBM 360/370 architecture.  The IBM System/370 Principles of Operation (POPS) is the base level document.  I am  using GA22-7000-5 (Fifth Edition, August 1976).

I first became interested in programming without an operating system  in 1975.  I was learning to program on a IBM 360 Model 20.  The model 20 was a very limited version of the 360 architecture.  It was a half-word machine and only had eight half-word registers.  The system I was using had a total of 12K of memory.  It did have a 2311 disk and a Disk Operating System (DOS).  I was programming in assembler and quickly found that I didn’t have much of the 12K of memory left over after loading in the operating system routines.

I decided that I needed to learn how to live without the resident DOS code.  I began to experiment and learn the basics.  The biggest issue was how to do Input/Output (I/O).  I quickly learned how to access the various devices using Channel Command Words (CCW).  The 360/20 didn’t use SIO (Start I/O) – it used an instruction called XIO (eXecute I/O) which did pretty much the same as SIO.  It also used an instruction called TIOB (Test I/O and Branch) which combined the function of  TIO (Test I/O) with a branch instruction.

From then on I used the Model 20 mostly without any Operating System.  This fun all came to an end when I moved on to larger systems running production applications under more complex operating systems (MVT, MFT, VS1, SVS, and MVS).

In the early 1980’s I was a systems programmer at a facility upgrading from a 370/158 to an 3033.  When the upgrade was completed the 370/158 remained in the computer room and was powered up to serve as a backup in case there were problems with the new processor.  There were no I/O devices connected to the 158 except for the integrated operator console.

Since the machine was just sitting in the corner of the room idling I decided to start programming it through the operator console using the Storage Alter function.

I began with very simple programs which evolved into larger, more complex programs over time.

When I left the 158 behind I lost the ability to program a 370 mainframe at the bare metal level until years later when I discovered the Hercules emulator.

With Hercules I now have my own personal IBM mainframe to once again play with.  Not only do I have a mainframe but I have my choice of peripheral devices to attach.

One final question – what does TXXOS mean?  When I first started playing with bare metal programming on Hercules I called my mini-operating system TXOS.  It was a bit of an inside joke on a “very short” OS.  When I decided to register a domain name I picked TXXOS.com – bottom line is it really doesn’t mean anything but I needed a domain name.

[ Next – Card Loader]