The interruption is a mechanism to signal the CPU when certain conditions exist. For I\/O interruptions the CPU is signaled when some event happens with an I\/O device such as I\/O operation complete or an error condition. \u00a0By using interruptions the CPU can initiate an I\/O operation and does not have to\u00a0continuously\u00a0check the status to see if it has completed. \u00a0Instead when the I\/O operation is complete the CPU will be signaled with an interrupt.<\/p>\n
There are several classes of interrupts defined in the System 370 architecture. \u00a0Each interrupt class has two specific locations in low memory used to hold PSWs. \u00a0When an interrupt occurs the current CPU PSW is stored in the Old PSW location for the interrupt class and is replaced with the value of the New PSW location.<\/p>\n
By loading a New PSW the state of the CPU is changed enabling the interruption condition to be handled. \u00a0When interruption handling is complete the Old PSW can be used to restore execution of the interrupted program.<\/p>\n
Some interruptions can be “Masked” – that is ignored depending on settings in the current PSW. \u00a0For example while an I\/O interruption is being processed all other I\/O interruptions should be masked until completion of the current I\/O interruption processing.<\/p>\n
The classes of interruptions are:<\/p>\n
Machine-Check Interruption<\/strong> Indicates an equipment malfunction. \u00a0When this\u00a0interruption occurs the Old PSW is stored in location 48 and a new PSW is fetched from location 112.<\/p>\n Program Interruption <\/strong>Results from an error during the execution of a program (such as an invalid operation code or attempt to execute a\u00a0privileged\u00a0instruction while in\u00a0problem\u00a0state). \u00a0When this\u00a0interruption occurs the Old PSW is stored in location 40 and a new PSW is fetched from location 104.<\/p>\n Supervisor Call Interruption<\/strong> Occurs when a Supervisor Call (SVC) instruction is executed.\u00a0When this\u00a0interruption occurs the Old PSW is stored in location 32 and a new PSW is fetched from location 96.<\/p>\n External Interruption<\/strong> Signals the CPU to conditions outside the system. \u00a0These interruptions include the operator pressing the Interrupt Key or when the Interval Timer is decremented and goes from a positive value to a negative value. \u00a0When this\u00a0interruption occurs the Old PSW is stored in location 24 and a new PSW is fetched from location 88.<\/p>\n Input\/Output Interruption <\/strong>Allows the CPU to be notified of various conditions for I\/O devices and channels. \u00a0When this\u00a0interruption occurs the Old PSW is stored in location 56 and a new PSW is fetched from location 120. \u00a0In addition a Channel Status Word (CSW) is stored at location 64.<\/p>\n Restart Interruption <\/strong>Allows the CPU to respond to an interruption generated by the operator pressing the restart key. \u00a0When this\u00a0interruption occurs the Old PSW is stored in location 8 and a new PSW is fetched from location 0 (zero).<\/p>\n [Next – Input Output Basics]<\/a><\/p>\n","protected":false},"excerpt":{"rendered":" The interruption is a mechanism to signal the CPU when certain conditions exist. For I\/O interruptions the CPU is signaled when some event happens with an I\/O device such as I\/O operation complete or an error condition. \u00a0By using interruptions … Continue reading