We can now IPL our Nucleus but if everything works correctly we simply idle waking up each time the Interval Timer expires, look for new work – which will never appear, and then wait again. \u00a0To make things a little more interesting we can add additional TCB’s in the TXXDINIT (Dispatcher\u00a0initialization routine). \u00a0It is a pretty simple process. \u00a0We simply need to define an additional TCB and RB and then add them onto the TCB chain that begins with the Wait Task TCB.<\/p>\n
00000 19 USING @RB,R5\r\n 20 *\r\n000016 4150 C158 00158 21 LA R5,RB1\r\n00001A D203 5008 C090 00008 00090 22 MVC RBPSW(4),=X'FF000000'\r\n000020 4110 C310 00310 23 LA R1,EXIT\r\n000024 5010 500C 0000C 24 ST R1,RBPSW+4\r\n000028 4110 C0F8 000F8 25 LA R1,TCB1\r\n00002C 5010 4000 00000 26 ST R1,TCBNEXT\r\n000030 1841 27 LR R4,R1\r\n000032 D207 4018 5008 00018 00008 28 MVC TCBPSW,RBPSW\r\n000038 5050 4008 00008 29 ST R5,TCBRB<\/pre>\nWe set the initial RB PSW to be enabled for interrupts and then set the instruction address to a routine called EXIT.<\/p>\n
000310 0A03 178 EXIT SVC 3<\/pre>\nThe EXIT routine is pretty simple. \u00a0We issue a SVC 3. \u00a0This should drive our SVC interrupt handler, our SVC 3 routine and our Exit Routine. \u00a0If all is well the RB and TCB will be terminated resulting in only the Wait Task remaining. \u00a0Although it is not terribly exciting it does test quite a bit of code.<\/p>\n
Now we can add another TCB and we will let it issue a Wait SVC to test the associated code.<\/p>\n
00003C 4150 C208 00208 31 LA R5,RB2\r\n000040 D203 5008 C090 00008 00090 32 MVC RBPSW(4),=X'FF000000'\r\n000046 4110 C308 00308 33 LA R1,WAIT\r\n00004A 5010 500C 0000C 34 ST R1,RBPSW+4\r\n00004E 4110 C1A8 001A8 35 LA R1,TCB2\r\n000052 5010 4000 00000 36 ST R1,TCBNEXT\r\n000056 1841 37 LR R4,R1\r\n000058 D207 4018 5008 00018 00008 38 MVC TCBPSW,RBPSW\r\n00005E 5050 4008 00008 39 ST R5,TCBRB<\/pre>\nNow we add another TCB and this time our instruction address points to a routine called WAIT.<\/p>\n
000308 172 WAIT DS 0H\r\n000308 05C0 173 BALR R12,0\r\n 0030A 174 USING *,R12\r\n 175 *\r\n00030A 4110 C00A 00314 176 LA R1,ECB\r\n00030E 0A01 177 SVC 1\r\n000310 0A03 178 SVC 3\r\n000314 00000000 179 ECB DC F'0'<\/pre>\nThe WAIT routine needs to establish a Base Register. \u00a0We then point Register 1 to an ECB and issue the SVC call for the Wait SVC. \u00a0When we IPL now we should have our previous TCB that terminates leaving the Wait Task and this TCB on the TCB chain. \u00a0We then wait forever in our idle loop. \u00a0It does serve to test the first half of our Wait routine.<\/p>\n
Now we can add a third task that will count down and issue a Post to the ECB.<\/p>\n
000062 4150 C2B8 002B8 41 LA R5,RB3\r\n000066 D203 5008 C090 00008 00090 42 MVC RBPSW(4),=X'FF000000'\r\n00006C 4110 C318 00318 43 LA R1,TIMER\r\n000070 5010 500C 0000C 44 ST R1,RBPSW+4\r\n000074 4110 C258 00258 45 LA R1,TCB3\r\n000078 5010 4000 00000 46 ST R1,TCBNEXT\r\n00007C 1841 47 LR R4,R1\r\n00007E D207 4018 5008 00018 00008 48 MVC TCBPSW,RBPSW\r\n000084 5050 4008 00008 49 ST R5,TCBRB<\/pre>\nThe PSW for this task points to a routine called TIMER.<\/p>\n
000318 181 TIMER DS 0H\r\n000318 05C0 182 BALR R12,0\r\n 0031A 183 USING *,R12\r\n00031A 5810 C04A 00364 184 L R1,TIMECT\r\n00031E 4120 0001 00001 185 LA R2,1\r\n000322 1B12 186 SR R1,R2\r\n000324 1211 187 LTR R1,R1\r\n000326 4780 C036 00350 188 BZ TIMEPOST<\/pre>\nThe TIMER routine establishes a base register and then loads a counter. \u00a0One is subtracted from the value of the counter and it is stored back. \u00a0If the value of the counter has gone to zero we branch to Post the ECB.<\/p>\n
00032A 5010 C04A 00364 189 ST R1,TIMECT\r\n00032E 5810 0010 00010 190 L R1,16 CVT\r\n000332 5810 1000 00000 191 L R1,CVTCTCB-@CVT(,R1)\r\n000336 50C0 101C 0001C 192 ST R12,TCBPSW-@TCB+4(,R1)\r\n00033A 50C0 1050 00050 193 ST R12,TCBREG12-@TCB(,R1)\r\n00033E 5810 0010 00010 194 L R1,16\r\n000342 5820 1004 00004 195 L R2,CVTTASKQ-@CVT(,R1)\r\n000346 5020 1000 00000 196 ST R2,CVTCTCB-@CVT(,R1)\r\n00034A 8200 C046 00360 197 LPSW TIMEPSW\r\n00034E 07FC 198 BR R12<\/pre>\nIf the counter is not zero we locate the current TCB and store Register 12 into the TCB as both R12 and the PSW instruction address. \u00a0This will cause these values to be loaded when the TCB is redispatched. \u00a0When then set the Wait Task TCB as the current TCB and load a enabled wait PSW.<\/p>\n
000350 199 TIMEPOST DS 0H\r\n000350 5810 C04E 00368 200 L R1,=A(ECB)\r\n000354 4100 0000 00000 201 LA R0,0\r\n000358 0A02 202 SVC 2\r\n00035A 0A03 203 SVC 3\r\n000360 204 DS 0D\r\n000360 FF020000 205 TIMEPSW DC AL1(255,2,0,0)\r\n000364 00001000 206 TIMECT DC A(X'1000')<\/pre>\nWhen the counter goes to zero we issue a Post SVC to post the ECB and then exit via SVC 3. \u00a0This should cause our second TCB to become dispatchable. \u00a0It should wake up and exit via SVC 3.<\/p>\n
Our counter is the address portion of the enabled wait PSW. \u00a0This gives us a visual indication on the Hercules console that something is really happening.<\/p>\n
We now have the basics of process management implemented in our TXXOS Operating System!<\/p>\n
[Next – I\/O Management<\/a>]<\/p>\n","protected":false},"excerpt":{"rendered":"
We can now IPL our Nucleus but if everything works correctly we simply idle waking up each time the Interval Timer expires, look for new work – which will never appear, and then wait again. \u00a0To make things a little … Continue reading