On entry to the P0st Routine Register 1 should point to an ECB and Register 0 contains a post code that is stored into the ECB. \u00a0The Post Routine is either called by the SVC 2 front end or directly through a branch entry.<\/p>\n
000000 13 TXXPOST CSECT ,\r\n 00000 14 USING TXXPOST,R15 ESTABLISH BASE REGISTER\r\n 15 *\r\n000000 5400 F080 00080 16 N R0,=A(X'3FFFFFFF') CLEAR WAIT\/POST BITS\r\n000004 5600 F084 00084 17 O R0,=A(X'40000000') SET POST BIT\r\n000008 5820 1000 00000 18 L R2,0(,R1) GET RB ADDRESS\r\n 19 *\r\n00000C 9180 1000 00000 20 TM 0(R1),X'80' IS ECB WAITING\r\n000010 47E0 F064 00000 21 BNO POST901 NO - BRANCH<\/pre>\nFirst we clean up the post code since the first two bits are reserved for the Wait and Post bit. \u00a0We then set the Post Bit (x’40’) to complete the post code. \u00a0The RB address pointer is loaded into R2 and then a test is done to see if a RB is waiting on the ECB. \u00a0If no RB is currently waiting we only need to store the post code into the ECB and exit.<\/p>\n
000014 5000 1000 00000 23 ST R0,0(,R1) UPDATE ECB CONTENTS\r\n000018 5420 F088 00088 24 N R2,=A(X'00FFFFFF') CLEAN UP 24 BIT\r\n00001C 5810 0010 00010 25 L R1,16 CVT\r\n000020 5810 1004 00004 26 L R1,CVTTASKQ-@CVT(,R1) GET TASK QUEUE\r\n000024 5810 1000 00000 27 L R1,TCBNEXT-@TCB(,R1) SKIP OVER WAIT TASK\r\n000028 28 POST010 DS 0H\r\n000028 1211 29 LTR R1,R1 END OF TCB CHAIN ?\r\n00002A 4780 F06A 0006A 30 BZ POST902 YES - RB TO POST NOT FOUND\r\n00002E 5830 1008 00008 31 L R3,TCBRB-@TCB(,R1) GET RB ADDRESS\r\n000032 32 POST020 DS 0H\r\n000032 1233 33 LTR R3,R3 END OF RB LIST\r\n000034 4780 F046 00046 34 BZ POST030 YES - NEXT TCB\r\n 35 *\r\n000038 1923 36 CR R2,R3 RB TO POST ?\r\n00003A 4780 F04E 0004E 37 BE POST040 YES - GO POST IT\r\n 38 *\r\n00003E 5830 3000 00000 39 L R3,RBNEXT-@RB(,R3) NEXT RB\r\n000042 47F0 F032 00032 40 B POST020 AND LOOP BACK\r\n 41 *\r\n000046 43 POST030 DS 0H\r\n000046 5810 1000 00000 44 L R1,TCBNEXT-@TCB(,R1) NEXT TCB\r\n00004A 47F0 F028 00028 45 B POST010 AND LOOP BACK<\/pre>\nIf there is a RB waiting on the ECB we need to validate the RB address. \u00a0We do this by scanning through the TCB chain looking at each RB chained to each TCB. \u00a0If the RB address in the ECB is not matched to a RB chained to a TCB we branch to generate an Abend.<\/p>\n
00004E 48 POST040 DS 0H\r\n00004E 9200 3004 00004 49 MVI RBWTCNT-@RB(R3),0 CLEAR WAIT COUNT FOR RB\r\n 50 *\r\n000052 5830 1008 00008 51 L R3,TCBRB-@TCB(,R1) POINT TO TOP RB FOR TCB\r\n000056 9500 3004 00004 52 CLI RBWTCNT-@RB(R3),0 WAITING ?\r\n00005A 4770 F062 00062 53 BNE POST050 YES - NOTHING TO UPDATE\r\n 54 *\r\n00005E 947F 1004 00004 55 NI TCBFLGS-@TCB(R1),X'FF'-TCBFWAIT CLEAR WAIT FLAG\r\n 56 *\r\n000062 57 POST050 DS 0H\r\n000062 07FE 58 BR R14 RETURN TO CALLER<\/pre>\nOnce the RB address is validated we can clear the Wait Count in the RB. \u00a0If the RB at the top of the chain we can clear the Wait Flag in the TCB making it dispatchable one again.<\/p>\n
000064 62 POST060 DS 0H\r\n000064 5000 1000 00000 63 ST R0,0(,R1) UPDATE ECB CONTENTS\r\n000068 07FE 64 BR R14 RETURN TO CALLER<\/pre>\nThe ECB is not currently being waited upon so we just store the post code and exit.<\/p>\n
00006A 66 POST902 DS 0H\r\n00006A 5810 F08C 0008C 67 L R1,=A(X'102') ABEND CODE\r\n00006E 47F0 F072 00072 68 B POST999\r\n 69 *\r\n000072 71 POST999 DS 0H\r\n 72 @CALL ABEND\r\n000072 58F0 0014 00014 73+ L R15,20 MVT ADDRESS\r\n000076 58F0 F020 00020 74+ L R15,MVTABEND-@MVT(,R15) ROUTINE ADDRESS\r\n00007A 05EF 75+ BALR R14,R15<\/pre>\nHere we set the Abend code and call the Abend routine if the RB address in the ECB was not valid.<\/p>\n
[Next – TXXGMAIN, GXXFMAIN, TXXABEND<\/a>]<\/p>\n","protected":false},"excerpt":{"rendered":"
On entry to the P0st Routine Register 1 should point to an ECB and Register 0 contains a post code that is stored into the ECB. \u00a0The Post Routine is either called by the SVC 2 front end or directly … Continue reading