There is not branch entry for Wait. \u00a0It is only entered through a SVC call. \u00a0On entry R4 is the address of the TCB and R5 is the address of the current RB which is always true for any SVC routine. \u00a0Register 1 is a pointer to either an ECB or a list of ECB’s. \u00a0If the high order bit of R1 is zero it is the address of a single ECB. \u00a0If the high order bit is one then it is the address of a list of pointers to ECB’s. \u00a0The last pointer in the list must have the high order bit set to one.<\/p>\n
000000 11 S001WAIT CSECT ,\r\n000000 18CF 12 LR R12,R15 ESTABLISH\r\n 00000 13 USING S001WAIT,R12 BASE REGISTER\r\n 14 *\r\n 00000 15 USING @TCB,R4\r\n 00000 16 USING @RB,R5\r\n 17 *\r\n000002 18A1 18 LR R10,R1 COPY PARM LIST\r\n000004 18B1 19 LR R11,R1 COPY PARM LIST\r\n000006 1211 20 LTR R1,R1 CHECK FOR ECB OR LIST\r\n000008 47D0 C048 00048 21 BNP LIST BRANCH IF LIST OF ECB'S<\/pre>\nAfter initial setup the high-order bit of Register 1 is checked using the Load Test Register instruction. \u00a0If the high order bit is one then LTR will indicate a negative value. \u00a0If it is zero then LTR will indicate positive.<\/p>\n
00000C 23 WAIT010 DS 0H\r\n00000C 9180 1000 00000 24 TM 0(R1),X'80' IS ECB ALREADY WAITING\r\n000010 4710 C0E8 000E8 25 BO WAIT900 YES - ABEND\r\n 26 *\r\n000014 9140 1000 00000 27 TM 0(R1),X'40' ECB ALREADY POSTED\r\n000018 4710 C03E 0003E 28 BO WAIT020 YES - NO NEED TO WAIT\r\n 29 *\r\n00001C 1825 30 LR R2,R5 RB ADDRESS\r\n00001E BF28 C0FC 000FC 31 ICM R2,B'1000',=X'80' SET WAIT BIT\r\n000022 5020 1000 00000 32 ST R2,0(,R1) SAVE INTO ECB\r\n 33 *\r\n000026 9201 5004 00004 34 MVI RBWTCNT,1 SET WAIT COUNT TO ONE\r\n00002A 9680 4004 00004 35 OI TCBFLGS,TCBFWAIT SET WAIT BIT\r\n 36 *\r\n00002E 5810 0014 00014 37 L R1,20 MVT ADDRESS\r\n000032 5810 1024 00024 38 L R1,MVTEXIT-@MVT(,R1) EXIT ROUTINE\r\n000036 5010 401C 0001C 39 ST R1,TCBPSW+4 MAKE IT RESUME POINT FROM WAIT\r\n00003A 5010 405C 0005C 40 ST R1,TCBREG15 SET R15 TO EP AT RESUME\r\n 41 *\r\n00003E 42 WAIT020 DS 0H\r\n00003E 58F0 0014 00014 43 L R15,20 MVT ADDRESS\r\n000042 58F0 F004 00004 44 L R15,MVTDISP-@MVT(,R15) DISPATCHER ADDRESS\r\n000046 07FF 45 BR R15<\/pre>\nFor a single ECB we begin by checking to see if the wait bit x’80’ is already set indicating the ECB is being waited on by another RB. \u00a0If it is set we branch to generate an Abend. \u00a0Next we check to see if the post bit x’40’ is set. \u00a0It is possible that the ECB was posted as complete before the Wait SVC was issued. \u00a0If it is already posted then we can just exit without waiting.<\/p>\n
If we need to wait we place the address of our RB into the ECB and set the wait bit. \u00a0We also set the wait count in the RB to one. \u00a0Currently we allow only a wait count of one but have the option of changing this later. \u00a0Since we set the wait count in top RB we also need to set the wait bit in the TCB so the Dispatcher will not dispatch this TCB until the ECB is posted and the wait count in the RB is cleared.<\/p>\n
Finally we get the address of the Exit routine and use it to update the contents of the TCB before branching to the Dispatcher. \u00a0We branch to the Dispatcher instead of the Exit routine because we want to interrupt execution of this RB at this point until the ECB has been posted. \u00a0If we branched to the Exit routine control would immediately be returned to the location immediately following the SVC 1. \u00a0To cause the wait we have set the Wait Bit in the TCB Flags so the TCB will not be dispatched. \u00a0When the post routine clears the Wait Bit the Dispatcher will at some point transfer control to this TCB. \u00a0When that happens we need to branch to the Exit Routine so control is returned to the caller of the SVC. \u00a0To accomplish this we set the PSW to point to the Exit Routine. \u00a0We must also replace the contents of Register 15 with the address of the Exit Routine. \u00a0Now when the Wait Bit is cleared and the Dispatcher transfers control to the TCB the PSW and register will be loaded from the TCB resulting in a branch to the Exit Routine.<\/p>\n
000048 49 LIST DS 0H\r\n000048 50 LIST010 DS 0H\r\n000048 5810 A000 00000 51 L R1,0(,R10) GET ECB ADDRESS\r\n00004C 9180 1000 00000 52 TM 0(R1),X'80' ECB ALREADY WAITING?\r\n000050 4710 C0E8 000E8 53 BO WAIT900 YES - ABEND\r\n 54 *\r\n000054 9180 A000 00000 55 TM 0(R10),X'80' END OF LIST\r\n000058 4710 C064 00064 56 BO LIST020\r\n 57 *\r\n00005C 41A0 A004 00004 58 LA R10,4(,R10) NEXT ECB IN LIST\r\n000060 47F0 C048 00048 59 B LIST010 LOOP BACK<\/pre>\nProcessing a list of ECB’s is pretty much the same process but what have to loop through the list. \u00a0We begin by looping through the list to verify none of the ECB’s have the Wait Bit set. \u00a0If we find an ECB with the Wait Bit set we branch to Abend.<\/p>\n
000064 63 LIST020 DS 0H\r\n000064 18AB 64 LR R10,R11 START OVER\r\n000066 65 LIST030 DS 0H\r\n000066 5810 A000 00000 66 L R1,0(,R10) GET ECB ADDRESS\r\n00006A 9140 1000 00000 67 TM 0(R1),X'40' ALREADY POSTED ?\r\n00006E 4710 C03E 0003E 68 BO WAIT020 YES - NO NEED TO WAIT\r\n 69 *\r\n000072 9180 A000 00000 70 TM 0(R10),X'80' END OF LIST\r\n000076 4710 C082 00082 71 BO LIST040\r\n 72 *\r\n00007A 41AA 0004 00004 73 LA R10,4(R10) NEXT ECB IN LIST\r\n00007E 47F0 C066 00066 74 B LIST030 LOOP BACK<\/pre>\nNext we check to see if any of the ECB’s in the list are already posted. \u00a0If any one of the ECB’s has been posted we don’t need to wait.<\/p>\n
000082 78 LIST040 DS 0H\r\n000082 18AB 79 LR R10,R11 START OVER AT TOP OF LIST\r\n000084 1825 80 LR R2,R5 RB ADDRESS\r\n000086 BF28 C0FC 000FC 81 ICM R2,B'1000',=X'80' SET WAIT BIT\r\n00008A 82 LIST050 DS 0H\r\n00008A 5810 A000 00000 83 L R1,0(,R10) GET ECB ADDRESS\r\n00008E 5020 1000 00000 84 ST R2,0(,R1) SET ECB CONTENTS\r\n000092 9180 A000 00000 85 TM 0(R10),X'80' END OF LIST\r\n000096 4710 C0A2 000A2 86 BO LIST060\r\n 87 *\r\n00009A 41A0 A004 00004 88 LA R10,4(,R10) NEXT ECB IN LIST\r\n00009E 47F0 C08A 0008A 89 B LIST050 LOOP BACK<\/pre>\nNext we loop through the list and place the address of the RB into each ECB while we also set the Wait Bit.<\/p>\n
0000A2 92 LIST060 DS 0H\r\n0000A2 9201 5004 00004 93 MVI RBWTCNT,1 SET WAIT COUNT TO ONE\r\n0000A6 9680 4004 00004 94 OI TCBFLGS,TCBFWAIT SET WAIT BIT\r\n 95 *\r\n0000AA 4110 C0C4 000C4 96 LA R1,LIST070 RESUME HERE AFTER WAIT POSTED\r\n0000AE 5010 401C 0001C 97 ST R1,TCBPSW+4 MAKE IT RESUME POINT FROM WAIT\r\n 98 *\r\n0000B2 50B0 4024 00024 99 ST R11,TCBREG1 R1 WILL POINT TO ECB LIST\r\n0000B6 50C0 4050 00050 100 ST R12,TCBREG12 R12 WILL CONTAIN BASE ADDRESS\r\n 101 *\r\n0000BA 58F0 0014 00014 102 L R15,20 MVT ADDRESS\r\n0000BE 58F0 F004 00004 103 L R15,MVTDISP-@MVT(,R15) DISPATCHER ADDRESS\r\n0000C2 07FF 104 BR R15<\/pre>\nNow we set up our branch to the Dispatcher. \u00a0Like before we set the RB Wait Count and the TCB Wait Flag. \u00a0Instead of setting up for a branch to the Exit Routine this time we come back to our code. \u00a0We set this up by updating the PSW in the TCB. \u00a0We also store Register 1 and Register 12 in the TCB so they will be available when the TCB is once again dispatched.<\/p>\n
0000C4 108 LIST070 DS 0H\r\n0000C4 18A1 109 LR R10,R1 POINT TO ECB LIST\r\n0000C6 110 LIST080 DS 0H\r\n0000C6 5810 1000 00000 111 L R1,0(,R1) ECB ADDRESS\r\n0000CA 947F 1000 00000 112 NI 0(R1),X'FF'-X'80' TURN OFF WAIT BIT\r\n 113 *\r\n0000CE 9180 A000 00000 114 TM 0(R10),X'80' END OF LIST\r\n0000D2 4710 C0DE 000DE 115 BO LIST090\r\n 116 *\r\n0000D6 41A0 A004 00004 117 LA R10,4(,R10) NEXT ECB PTR\r\n0000DA 47F0 C0C6 000C6 118 B LIST080 LOOP BACK FOR NEXT ECB<\/pre>\nWhen we get redispatched after the post we need to go through the ECB list and turn off the waiting bit for each ECB in the list. \u00a0Once that is done we branch to the Exit Routine.<\/p>\n
0000DE 121 LIST090 DS 0H\r\n0000DE 58F0 0014 00014 122 L R15,20 MVT ADDRESS\r\n0000E2 58F0 F024 00024 123 L R15,MVTEXIT-@MVT(,R15) EXIT ROUTINE\r\n0000E6 07FF 124 BR R15\r\n 125 *\r\n0000E8 127 WAIT900 DS 0H\r\n0000E8 5810 C0F8 000F8 128 L R1,=A(X'101') ABEND CODE\r\n 129 @CALL ABEND\r\n0000EC 58F0 0014 00014 130+ L R15,20 MVT ADDRESS\r\n0000F0 58F0 F020 00020 131+ L R15,MVTABEND-@MVT(,R15) ROUTINE ADDRESS\r\n0000F4 05EF 132+ BALR R14,R15<\/pre>\nIf a ECB with the Wait Bit was passed to the Wait SVC routine an Abend x’101′ will be issued.<\/p>\n
[Next – SVC 2 – Post<\/a>]<\/p>\n","protected":false},"excerpt":{"rendered":"
There is not branch entry for Wait. \u00a0It is only entered through a SVC call. \u00a0On entry R4 is the address of the TCB and R5 is the address of the current RB which is always true for any SVC … Continue reading