The Program Status Word (PSW) contains information about the current execution state of the processor. \u00a0Certain actions cause the complete PSW to be stored or loaded. \u00a0Others operate on only a portion of the PSW.<\/p>\n
The Load PSW instruction (LPSW) will load a new value into the PSW and replace the old contents. \u00a0Interrupts cause the current PSW contents to be stored at a specific location and a new PSW to be loaded. \u00a0The locations for storing the old PSW and fetching the new PSW are defined in low storage with the actual address depending on the specific interrupt.<\/p>\n
In 370 mode there are two different forms of the PSW – Basic Control (BC) and Extended Control (EC). \u00a0The BC PSW is essentially the same format as initially introduced on the System 360. \u00a0When bit 12 of the PSW is zero the PSW is in BC mode. \u00a0For now we will only concern ourselves with the BC PSW.<\/p>\n
The BC PSW consists of 64 bits (8 bytes or 2 words) with the following layout:<\/p>\n
Bits 0-5 Channel Masks 0-5<\/pre>\nBit 6 Input\/Output Mask (IO)<\/pre>\nBit 7 External Mask (E)<\/pre>\nBits 8-11 Protection Key<\/pre>\nBit 12 BC\/EC Control<\/pre>\nBit 13 Machine Check Mask (M)<\/pre>\nBit 14 Wait State (W)<\/pre>\nBit 15 Problem State (P)<\/pre>\nBits 16-31 Interruption Code<\/pre>\nBits 32-33 Instruction Length Code (ILC)<\/pre>\nBits 34-35 Condition Code (CC)<\/pre>\nBits 36-39 Program Mask<\/pre>\nBits 40-63 Instruction Address<\/pre>\nChannel Masks 0-5 <\/strong>(Bits 0-5) Control whether the CPU \u00a0is enabled for I\/O interruptions from channels 0-5. \u00a0When the bit is zero the corresponding channel cannot cause an I\/O interruption. \u00a0When the bit is one an interruption can occur.<\/p>\n
Input\/Output Mask (IO) <\/strong>(Bit 6) Controls\u00a0whether\u00a0the CPU is enabled for I\/O interruptions from channels 6 and higher. \u00a0When the bit is zero these channels cannot cause an I\/O interruption. \u00a0When the bit is one interruptions may occur if the channel interruption is enabled in control register (CR) 2. \u00a0Setting the I\/O mask bit in the PSW to zero has the same effect as setting all the bits in CR 2 to zero. \u00a0Initially CR 2 contains a value of one in all bits therefore enabling all\u00a0interrupts\u00a0on channels 6 and higher when the IO Mask bit is set to one.<\/p>\n
External Mask (E)<\/strong> (Bit 7) Controls whether the CPU is enabled for external interruptions. \u00a0When set to one interruptions are enabled.<\/p>\n
Protection Key<\/strong> (Bits 8-11) The protection key is compared to the page storage key when storing to memory or when fetching and the page is protected against fetching. \u00a0A PSW protection key of zero can access any page.<\/p>\n
Extended Control Mode<\/strong> (Bit 12) Indicates the format of the PSW and the mode of operation of the CPU. \u00a0For Basic Control (BC) the bit is set to zero, for Extended Control (EC) the bit is set to one.<\/p>\n
Machine Check Mask (M)<\/strong> (Bit 13) Controls whether the CPU is enabled for machine check interruptions. \u00a0When set to one interruptions are enabled.<\/p>\n
Wait State (W)<\/strong> (Bit 14) When the Wait bit is set to one the CPU is in the wait state and no instructions are executed. \u00a0When set to zero it is in running state.<\/p>\n
Problem State (P)<\/strong> (Bit 15) When set to one the CPU is in problem state and any attempt to execute a\u00a0privileged\u00a0instruction will fail. \u00a0When set to zero the CPU is in supervisor state.<\/p>\n
Interruption Code<\/strong> (Bits 16-31) When an old PSW is stored as a result of a program, supervisor call, external or I\/O interruption these bits identify the cause of the interruption. \u00a0These bits are ignored when a new PSW is loaded.<\/p>\n
Instruction Length Code (ILC) <\/strong>(Bits 32-33) Indicates the length of the last executed instruction when a program or supervisor call interruption occurs or when a Branch And Link is executed. \u00a0The contents of these bits are ignored when a new PSW is loaded.<\/p>\n
Condition\u00a0Code (CC) <\/strong>(Bits 34-35) Condition code.<\/p>\n
Program Mask<\/strong> (Bits 36-39) Each bit is associated with a program\u00a0exception\u00a0interruption. When the bit is zero an interruption will not occur. \u00a0Bit 36: Fixed-point overflow. Bit 37: Decimal overflow. Bit 38: Exponent underflow. Bit 39: Significance.<\/p>\n
Instruction Address<\/strong> (Bits 40-63) Contains the address of the next instruction to be executed.<\/p>\n
[ Next – Interruptions ]<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"
The Program Status Word (PSW) contains information about the current execution state of the processor. \u00a0Certain actions cause the complete PSW to be stored or loaded. \u00a0Others operate on only a portion of the PSW. The Load PSW instruction (LPSW) … Continue reading