MVS 3.8 does no have any of the modern cross memory services available software or hardware.\u00a0 In order to communicate between address spaces some system level code must be used.\u00a0 Shared data can be placed into Common Service Area (CSA) storage which can be accessed by all address spaces.\u00a0 If address space A wants to send a message to address space B, address space A could copy the message into an area of CSA known by both A and B.\u00a0 The problem is how address space B knows the data is available.\u00a0 We could loop looking for changes but that would consume a lot of CPU time and would not be very efficient.\u00a0 We could look for changes and upon finding none we could wait some time interval before loooking again.\u00a0 If the delay interval is set too low a large amount of CPU time would still be consumed.\u00a0 If the interval is set too high the program becomes unresponsive since a delay is built in.<\/p>\n
The normal way to synchronize between multiple tasks is to use the WAIT\/POST functionality.\u00a0 A task issues a WAIT supervisor call pointing to an Event Control Block (ECB).\u00a0 The signaling task issues a POST supervisor call pointing to the same ECB to wake up the waiting task.\u00a0 This works very well inside a single address space but does not work across address spaces.<\/p>\n
MVS does provide a way to POST and ECB in another address space.\u00a0 Is is a little more complicated than simply using the POST macro.\u00a0 In addition to the SVC interface to POST, MVS also provides a Branch Entry.\u00a0 Using Branch Entry is more complicated and requires the caller to be in supervisor mode and key zero.\u00a0 It does have the advantage of allowing us to post and ECB in an address space other than our own.<\/p>\n
Below is a summary of the registers used as input for Branch Entry POST.<\/p>\n
R10 - POST Completion Code (to be placed into ECB)\r\nR11 - ECB Address (high order bit of register must be set to X'80')\r\nR12 - Error Return Address\r\nR13 - ASCB Address of address space containing ECB\r\nR14 - Linkage Return Address\r\nR15 - Entry Point (CVT0PT01)<\/pre>\nThe high order bit of register 11 determines if the request is a cross memory post.\u00a0 When calling the Branch Entry POST routine for a non-cross memory post we must hold the Local Lock.\u00a0 For a cross memory post we do not have to hold any locks but we must be aware that the contents all registers except register 9 will be destroyed.<\/p>\n
SRB Cross Memory Post<\/h2>\n
We now have enough to modify our simple SRB routine to post an ECB to signal a waiting task in another address space.\u00a0 We will begin by expanding our CSA storage map to include a parmameter list to be passed to the SRB routine.<\/p>\n
WKAREA DSECT , \r\nPARMLIST DS 0F PARAMETER LIST FOR SRB ROUTINE \r\nWAITECB DS A ADDRESS OF LOCAL ECB \r\nWAITASCB DS A ADDRESS OF WAITING ASCB \r\n* \r\nSRBAREA DS CL(44) \r\nSRBCODE DS CL(ENDSRTN-SRBRTN) \r\n* \r\n* \r\nWKLEN EQU *-WKAREA<\/pre>\nWe will pass two parameters to the SRB routine. The first is the address of the waiting ECB located in the private area and the second is the address of the ASCB for the waiting address space.\u00a0 When our SRB routine is dispatched the address of the parmaeter list will be contained in register 1.<\/p>\n
SRBRTN DS 0H \r\n LR R6,R15 SRB ROUTINE EP \r\n USING SRBRTN,R6 \r\n* \r\n LR R4,R1 SAVE PARM REGISTER \r\n USING PARMLIST,R4 \r\n* \r\n LR R9,R14 SAVE RETURN ADDRESS \r\n* \r\n* \r\n LA R10,X'7F' POST \r\n SLL R10,24 COMPLETION CODE \r\n* \r\n L R11,WAITECB ECB ADDRESS \r\n LA R1,X'80' SET \r\n SLL R1,24 HIGH-ORDER \r\n OR R11,R1 BIT \r\n* \r\n LA R12,POSTERR ERROR ROUTINE \r\n L R13,WAITASCB ASCB ADDRESS \r\n* \r\n L R15,CVTPTR CVT ADDRESS \r\n L R15,CVT0PT01-CVTMAP(,R15) POST BRANCH-ENTRY \r\n BALR R14,R15 \r\n* \r\n* \r\n BR R9 DONE - EXIT \r\n* \r\n* \r\nSRBCLEAN DS 0H SRB PURGE ROUTINE \r\n XC 0(SRBSIZE,R1),0(R1) \r\n BR R14 \r\n* \r\n* \r\nPOSTERR DS 0H POST ERROR ROUTINE \r\n BR R14 \r\n* \r\n* \r\n LTORG ,<\/pre>\nThe first thing we do is copy the address of the parm list into register 4.\u00a0 Next we save the return address in register 9 (this is because register 9 is the only register preserved when we call Branch Entry POST).\u00a0 Next we set our post code into register 10.\u00a0 It can be anything we want so I chose X’7F000000′ but it really doesn’t matter. Next we load the address of the ECB into register 11 and set the high order bit to X’80’ to indicate a cross memory post.\u00a0 The address of our Post Error Routine goes into R12 and the address of the ASCB for the task that is waiting goes into R13.\u00a0 All the remains is to get the address of the Branch Entry Post routine into register 15 and then call it.\u00a0 Upon return the contents of all registers except R9 will be lost.\u00a0 Since all we need to do is exit all we need is the return address we saved in R9.\u00a0 We also added our Post Error Routine which immediately returns to the caller.<\/p>\n
That’s it for the SRB routine but we still need some changes in our code that sets up and schedules the SRB.<\/p>\n
\r\n L R9,CVTPTR CVT ADDRESS \r\n L R9,CVTASVT-CVTMAP(,R9) ASVT ADDRESS \r\n L R9,ASVTENTY-ASVT(,R9) FIRST ASCB POINTER \r\n L R9,4(,R9) ASCB FOR ASID=0002 (JES2)<\/pre>\nWe could continue to schedule the SRB into our own address space and call the cross memory post routine but we really should schedule the SRB routine into a different address space so we really are doing a cross memory post.\u00a0 I chose to use the JES2 address space since it is always active and I can be pretty confident it will be in ASID x’0002′.\u00a0 Again it really doesn’t matter for now and any valid address space could be used.\u00a0 To find the JES2 ASCB we get the Address Space Vector Table address from the CVT.\u00a0 We then offset to the list of pointers to ASCBs.\u00a0 The first entry is ASID x’0001′, the second ASID x’002′, and so on.\u00a0 We take the address of the second ASCB which should be the addres space for JES2.\u00a0 We save this address in R9.<\/p>\n
ST R9,SRBASCB TARGET ASCB TO SCHEDULE TO<\/pre>\nNext we need to place the address of the ASCB\u00a0 for JES2 into the SRB so it will be scheduled there.<\/p>\n
\r\n LA R1,PARMLIST PARM LIST \r\n ST R1,SRBPARM \r\n* \r\n ST R8,WAITASCB SAVE OUR ASCB ADDRESS INTO PARMLIST\r\n* \r\n LA R1,LOCALECB \r\n ST R1,WAITECB<\/pre>\nNow we have to set up the parameter list for the SRB routine.\u00a0 We place the pointer to the parm list into the SRB control block.\u00a0 The address of the ASCB for our address space goes into the parameter list along with the address of an ecb.<\/p>\n
WAIT 1,ECB=LOCALECB WAIT FOR SRB TO COMPLETE<\/pre>\nNow instead of setting a delay we wait for our ECB to be posted by the SRB routine.<\/p>\n
LOCALECB DC F'0'<\/pre>\nHere is the ECB we will wait on (located in our private storage).<\/p>\n
IHAASVT ,<\/pre>\nFinally we need to include the mapping macro for the ASVT. With this we are done and our program can be compiled, link edited and we can run it. If everything goes as planned it should run very quickly.<\/p>\n
JOB 6755 $HASP373 SRB02 STARTED - INIT 12 - CLASS A - SYS TCS3 \r\nJOB 6755 15.39.08 0.00.00 0.00.00 0000 SRB02 MVSSP \r\nJOB 6755 15.39.08 0.00.00 0.00.00 0000 SRB02 ######## \r\nJOB 6755 $HASP395 SRB02 ENDED<\/pre>\n","protected":false},"excerpt":{"rendered":"MVS 3.8 does no have any of the modern cross memory services available software or hardware.\u00a0 In order to communicate between address spaces some system level code must be used.\u00a0 Shared data can be placed into Common Service Area (CSA) storage which can be accessed by all address spaces.\u00a0 If address space A wants to …<\/p>\n